Process for borderless stop in tin via formation

ABSTRACT

A method of forming via plugs in a semiconductor device, comprising the following steps. A semiconductor structure having an upper first oxide layer and at least two metal lines formed on the upper oxide layer are provided. The metal lines are spaced apart a predetermined distance and each having a lower barrier layer, a middle layer, and an upper etch stop layer. A second oxide layer is deposited over the first oxide layer and the pair of metal lines. An etch barrier layer is formed over the second oxide layer. The structure is planarized to form openings in the etch barrier layer over the metal lines. A third oxide layer is deposited and patterned over the planarized structure to form via openings through the etch barrier layer openings to the upper etch stop layers on the metal lines. Metal via plugs are formed in the via openings.

FIELD OF THE INVENTION

The present invention relates generally to forming via plugs insemiconductor devices, and more specifically to forming via plugs toborderless structure semiconductor devices.

BACKGROUND OF THE INVENTION

As the design rule for semiconductor devices constantly decreases,borderless structures, such as contacts, have been begun to be used topermit the further microminiaturization. However, the use of borderlessstructures requires a level and degree of accuracy in fabricating thesedevices that is not met to achieve acceptable yields. Misaligned viaopenings can create metal via plugs formed in contact with sidewalls ofmetal lines that degrade the electromigration of the metal via plugs.

U.S. Pat. No. 5,920,792 to Lin describes an etch stop over an HDP-CVDoxide layer. A first HDP-CVD oxide layer is formed over a metal wiringstructure having a gap. A second HDP-CVD oxide layer is formed over thefirst HDP-CVD oxide layer. The second HDP-CVD oxide layer having loweretching/depositing component ratio, and thus a higher CMP removal rate,than the first HDP-CVD oxide layer. A thin CMP passive layer may bedeposited over the second HDP-CVD oxide layer. The thin CMP passivelayer having the same etching/depositing component ratio as the secondHDP-CVD oxide layer. The structure is chemical-mechanically polished(CMP) wherein: the thin CMP passive layer minimizes dishing in therecessed areas and is removed; the second HDP-CVD oxide layer ispolished and removed by CMP until the first HDP-CVD oxide stop layer isreached resulting in an essentially planar surface.

U.S. Pat. 5,904,569 to Kitch describes a process of forming self-alignedvias in multi-metal integrated circuits using self-aligned metal pillarsto connect metal layers separated by a dielectric. The metal pillarscomprise a first aluminum (Al) layer, a middle titanium nitride (TiN)layer that acts as an etch stop layer, and an upper Al layer.

U.S. Pat. No. 5,891,799 to Tsui describes a method for making stackedand borderless via structures on multilevel metal interconnections forintegrated circuits.

U.S. Pat. No. 5,840,624 to Jang et al. describes a method for forming aborderless contact or via hole in which a thin silicon nitride layer isused as an etch stop to prevent attack of an underlying interleveldielectric (ILD) layer during the opening of the borderless contact orvia hole in an overlying ILD layer.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide amethod of forming self-aligned via plugs to borderless structures insemiconductor structures.

Another object of the present invention is to provide a method offorming self-aligned via plugs to borderless structures in semiconductorstructures using etch stop layers over the borderless structures.

A further object of the present invention is to provide a method offorming self-aligned via plugs to borderless structures in semiconductorstructures without the need to mask and etch the SiN etch stop layer.

Yet another object of the present invention is to provide a method offorming self-aligned via plugs to borderless structures in semiconductorstructures using a self-aligned SiN etch barrier that preventsinter-metal shorts otherwise due to via over-etch.

Other objects will appear hereinafter.

It has now been discovered that the above and other objects of thepresent invention may be accomplished in the following manner.Specifically, a semiconductor structure having an upper first oxidelayer and at least two metal lines formed on the upper oxide layer areprovided. The metal lines are spaced apart a predetermined distance andeach having a lower barrier layer, a middle layer, and an upper etchstop layer. A second oxide layer is deposited over the first oxide layerand the pair of metal lines. An etch barrier layer is formed over thesecond oxide layer. The structure is planarized to form openings in theetch barrier layer over the metal lines. A third oxide layer isdeposited and patterned over the planarized structure to form viaopenings through the etch barrier layer openings to the upper etch stoplayers on the metal lines. Metal via plugs are formed in the viaopenings.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the method of forming an liquid crystaldisplay lower substrate according to the present invention will be moreclearly understood from the following description taken in conjunctionwith the accompanying drawing in which like reference numerals designatesimilar or corresponding elements, regions and in which:

FIG. 1 illustrates in cross-sectional representation conventional viaplugs formed to a pair of borderless metal wires known to the inventor.

FIGS. 2 through 7 schematically illustrate in cross-sectionalrepresentation a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Problem Solved by the Invention

FIG. 1 illustrates a conventional via plug structure to borderless metalwires known by the inventor (not to be considered as prior art and notthe invention).

Semiconductor structure 110 includes an upper silicon oxide layer. Metallines 112, 114 are formed over semiconductor structure 110 and includelower barrier layers 116, 118, middle layers 117, 119, and upper TiNlayers 120, 122, respectively. Metal lines 112, 114 are spaced apartdistance 115 greater than or equal to 0.23 μm.

Metal line middle layers 117, 119 may be comprised of AlCu or AlSiCu.Lower barrier layers 116, 118 may be comprised of Ti, TiN, or Ti/TiN.Upper TiN or Ti/TiN layers 120, 122 function as etch stop layers.

A second oxide layer 124 is deposited and planarized over semiconductorstructure 110 and metal lines 112, 114.

A third oxide layer, or intermetal dielectric layer (IMD), 126 isdeposited, planarized, and patterned over second oxide layer 124 to formvia openings 128, 130. A not uncommon problem is that etching of secondoxide layer 124 to form via openings 128, 130 may etch through upper TiNlayers 120, 122 and gouge into middle layers 117, 119 of metal lines112, 114, respectively (not shown) which degrades the electromigration(EM) of metal via plugs 134, 136. This may be caused because variationsin the thickness of IMD layer 126 can introduce over-etching during theetching of via openings 128, 130. To reduce variations in via Rc(stopping TiN anti-reflective coating (ARC) 120, 122 will result in ahigher Rc, more over-etch is introduced to ensure consistency. If oxideis left over the TiN, the via Rc increases. Even a thick TiN layer canincrease Via Rc. If an overetch is used to remove all the oxide, theetch goes through the TiN and causes electromigration.

Further, as shown in FIG. 1, another problem occurs when, for example,via opening 128 is misaligned and second oxide layer 124 is partiallyetched exposing part of sidewall 132 of middle layer 117 of metal line112. When metal via plugs 134, 136 are formed within via openings 128,130, respectively, metal via plug 134 contacts sidewall 132 of middlelayer 117 of metal line 112 which also degrades the EM of metal viaplugs 134.

Preferred Embodiment of the Invention

The inventor has discovered a process of forming via plugs insemiconductor devices that (1) prevents misaligned via openings fromexposing a portion of the sidewalls of the underlying metal lines sothat when metal via plugs are formed within the via openings a portionof the metal via plugs do not come into contact with the underlyingmetal line thus preventing degradation of the EM of the metal via plugs;and (2) permits defining an SiN etch barrier without masking and etchingof the SiN etch barrier which greatly simplifies the process.

Accordingly as shown in FIG. 2, starting semiconductor structure 10includes an upper oxide layer and is understood to possibly include asemiconductor wafer or substrate, active and passive devices formedwithin the wafer, conductive layers and dielectric layers (e.g.,inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed overthe wafer surface. The term “semiconductor structure” is meant toinclude devices formed within a semiconductor wafer and the layersoverlying the wafer. Unless otherwise specified, all structures, layers,etc. may be formed or accomplished by conventional methods known in theprior art.

One or more two metal lines 12, 14 are formed over semiconductorstructure 10. If more than one line if formed, the lines are spacedapart a distance 15 greater than or equal to 0.23 μm, and morepreferably about 0.3 μm at gap 13. The upper surface of thesemiconductor structure can be a dielectric layer (e.g., interleveldielectric (ILD) or inter metal dielectric (IMD) layer) composed of anoxide, such as a doped oxide or oxynitride. Metal lines 12, 14 includelower barrier layers 16, 18, middle layers 17, 19, and upper etch stoplayers 20, 22, respectively.

It is obvious to one skilled in the art that even though metal line 12is shown in FIG. 2 as having a width less than that of metal line 14,the widths could be reversed, or both metal lines 12, 14 may have thesame width—either equal to the width of metal line 12 or metal line 14.

Middle layers 17, 19 are from about 4500 to 5500 Å thick, and morepreferably about 5000 Å thick, and may be comprised of AlSiCu and aremore preferably comprised of AlCu.

Lower barrier layers 16, 18 are from about 180 to 440 Å thick and morepreferably from about 200 to 400 Å thick, and may be comprised of Ti orTiN, and more preferably Ti/TiN. Barrier layers 16, 18 serve to preventdiffusion of middle layers 17, 19 into the upper oxide layer ofsemiconductor structure 10.

Upper etch stop layers 20, 22 are anti-reflective coatings from about280 to 370 Å thick, and more preferably from about 300 to 350 Å thick,and may be comprised of Ti, Ti/TiN and more preferably a TiNanti-reflective coating.

As shown in FIG. 3, one key step of the present invention is that oxidelayer 24 is deposited by a non-conformal, high density plasma (HDP)process to a depth just sufficient to fill gap 13 between metal lines12, 14 and may be up to a depth of about 6000 Å.

It is critical that an HPD process be used to form the layer 24. HPDprocesses include processing with low energy ions with a density equalto or greater than 1E12 cm⁻². HPD process that can be used to form layer24 include ICP, DPS, electron cyclotron resonance (ECR), SiH₄/O₂/Ar, orSiH₄/O₂/Ar/SiFe processes. Since the HDP process is non-conformal, thewidth of peak portions 21, 23 of HDP-oxide layer 24 over metal lines 12,14, respectively, mirror the width of metal lines 12, 14, and areself-aligned over metal lines 12,14, respectively. The importance ofwhich will become evident hereafter.

The HDP process may be conducted from about 320 to 370° C., and morepreferably about 350° C., using silane and O₂/Ar.

The HPD process is preferably preformed with a deposition to sputterratio between about 2.0 and 3.0.

HDP-oxide layer 24 may comprise HDP-silicon oxide or doped versionsthereof such as HDP-PSG or HDP-FSG.

As shown in FIG. 4, etch barrier layer 25 is deposited over HDP-oxidelayer 24 to a thickness of from about 950 to 1050 Å, and more preferably1000 Å. Etch barrier layer 25 may be comprised of H-rich silicon nitrideor Si-rich silicon nitride and more preferably SiN.

SiN etch barrier layer includes lower, flat portions 25 a, and raisedpeak portion 25 b over HDP-oxide peak 21 over metal line 12, and raisedpeak portion 25 c over HDP-oxide peak 23 over metal line 14.

As shown in FIG. 5, an oxide chemical-mechanical polishing (CMP) is thenconducted to polish and remove SiN etch barrier layer peak portions 25b, 25 c and HDP-oxide peak portions 21, 23, each over metal lines 12,14, respectively.

It is noted that since HDP-oxide peak portions 21, 23 are the same widthas, and self-aligned over, the underlying metal lines 12, 14 openings27, 29 formed by the oxide CMP in SiN etch barrier layer between flatportions 25 a are also self-aligned over metal lines 12, 14,respectively. The width of SiN etch barrier layer openings 27, 29 areslightly less than the width of metal lines 12, 14, respectively, bymore than about 5%, and more preferably from about 5 to 10%.

As shown in FIG. 6, cap oxide layer 26 is deposited and patterned overoxide layer 24 and SiN etch barrier layer flat portions 25 a to form viaopenings 28, 30. Via openings 28, 30 are designed to pass through SiNetch barrier layer openings 27, 29 and oxide layer 24 to expose TiNlayers 20, 22 with TiN layers 20, 22 acting as etch stop layers. Viaopenings 28, 30 are etched through the cap oxide layer 26 and preferablystop in the TiN layer 22. A photoresist layer (not shown) may be used tofor the via openings. The SiN etch barrier layers 25 a act as etchguides/stops. The etch preferably stops on the TiN layers 20 22 orwithin the TiN layers (removing some portion of the TiN layer, but notexposing the underlying metal layer.)

If a via opening is misaligned, such as, for example, via opening 28 asshown in FIG. 6, SiN etch barrier layer flat portion 25 a at 31 isresistant to the via opening 28, 30 etch and is not etched. Sinceopenings 27, 29 within SiN etch barrier layer are self-aligned overmetal lines 12, 14 and have a width slightly less than the width ofmetal lines 12, 14 parts 31 of SiN etch barrier layer flat portions 25 ashield the underlying edges 33 of metal lines 12, 14 and the portions ofoxide layer 24 there between.

Thus the design and process of the present invention eliminates thepossibility of a misaligned via opening 28, for example, from exposing aportion of a sidewall of middle AlCu layer 17 of metal line 12, forexample.

As shown in FIG. 7, a metal layer (not shown) is deposited over oxidelayer 26, filling via openings 28, 30, and planarized to form metal viaplugs 34, 36. Metal via plugs 34, 36 may be comprised of AlCu or Cu, andmore preferably tungsten (W).

Since any misaligned via opening 28 for example as shown in FIGS. 6 and7, is barred from penetrating parts 31 of SiN etch barrier layer flatportions 25 a, metal via plug 34, for example as shown in FIG. 7, doesnot contact any sidewall portion of middle AlCu layer 17 of metal line12. Thus the electromigration (EM) of W metal via plug 34 is notdegraded.

In summary, the process of the present invention improves theelectromigration of W metal via plugs 34, 36 by minimizing oreliminating direct contact between W metal via plugs 34, 36 and middleAlCu layer of metal lines 12, 14.

While particular embodiments of the present invention have beenillustrated and described, it is not intended to limit the invention,except as defined by the following claims.

I claim:
 1. A method of forming via plugs in a semiconductor device,comprising the steps of: providing a semiconductor structure having anupper first oxide layer and at least two metal lines formed on saidupper oxide layer; said metal lines being spaced apart a first distanceand each having a lower barrier layer, a middle layer, and an upper etchstop layer; depositing a second oxide layer over said first oxide layerand said pair of metal lines; said second oxide layer is non-conformal;forming an etch barrier layer over said second oxide layer; planarizingsaid structure to form openings in said etch barrier layer over saidmetal lines; depositing and patterning a third oxide layer over saidplanarized structure to form via openings through said etch barrierlayer openings to said upper etch stop layers on said metal lines; andforming metal via plugs in said via openings.
 2. The method of claim 1,wherein said metal lines are borderless metal lines.
 3. The method ofclaim 1, wherein said first distance between said metal lines is greaterthan about 0.23 μm.
 4. The method of claim 1, wherein said etch barrierlayer is comprised of a material selected from the group consisting ofSiN, SiON, H-rich silicon nitride, and Si-rich silicon nitride.
 5. Themethod of claim 1, wherein said lower barrier layer is comprised of amaterial selected from the group consisting of Ti, TiN, and Ti/TiN. 6.The method of claim 1, wherein said middle layer is comprised of amaterial selected from the group consisting of AlCu and AlSiCu.
 7. Themethod of claim 1, wherein said upper etch stop layer is ananti-reflective coating comprised of a material selected from the groupconsisting of TiN and Ti/TiN.
 8. The method of claim 1, wherein saidsecond oxide layer is formed by a high-density plasma (HDP) process. 9.The method of claim 1, wherein said second oxide layer is comprised of amaterial selected from the group consisting of HDP-oxide, HDP-FSG andHDP-PSG.
 10. The method of claim 1, wherein said metal lines comprisesaid lower barrier layer selected from the group consisting of Ti andTiN, said middle layer of AlCu, and said upper etch stop layer is a TiNARC.
 11. The method of claim 1, wherein said metal via plugs arecomprised of a metal selected from the group consisting of tungsten,aluminum, Cu, and AlCu.
 12. The method of claim 1, wherein said metallines comprise said lower barrier layer selected from the groupconsisting of Ti, TiN and Ti/TiN, a middle layer comprised of a materialselected from the group consisting of AlCu and AlSiCu, and said upperetch stop layer is an ARC selected from the group consisting of TiN andTi/TiN; said second oxide layer is an HDP-oxide selected from the groupconsisting of HDP-FSG and HDP-PSG; said etch barrier layer comprises amaterial selected from the group consisting of SiN, (SiON), H-richsilicon nitride, and Si-rich silicon nitride; and said metal via plugscomprise a material selected from the group consisting of tungsten,aluminum, and AlCu.
 13. A method of forming via plugs in a semiconductordevice, comprising the steps of: providing a semiconductor structurehaving an upper first oxide layer and at least two metal lines formed onsaid upper oxide layer; said metal lines being spaced apart greater thatabout 0.23 μm and each having a lower barrier layer and an upper etchstop layer; depositing a second oxide layer over said first oxide layerand said pair of metal lines by a high-density plasma (HDP) process;forming an etch barrier layer over said second oxide layer; planarizingsaid structure using a chemical-mechanical polish process to formopenings in said etch barrier layer over said metal lines; depositingand patterning a third oxide layer over said planarized structure toform via openings through said etch barrier layer openings to said upperetch stop layers on said metal lines; and forming metal via plugs insaid via openings.
 14. The method of claim 13, wherein said metal linesare borderless metal lines.
 15. The method of claim 13, wherein saidetch barrier layer is comprised of a material selected from the groupconsisting of SiN, SiON, H-rich SiN and Si-rich SiN.
 16. The method ofclaim 13, wherein said middle layer is comprised of a material selectedfrom the group consisting of AlCu and AlSiCu.
 17. The method of claim13, wherein said lower barrier layer is comprised of a material selectedfrom the group consisting of Ti, TiN, and Ti/TiN.
 18. The method ofclaim 13, wherein said upper etch stop layer is an anti-reflectivecoating comprised of a material selected from the group consisting ofTiN, Ti, and Ti/TiN.
 19. The method of claim 13, wherein said secondoxide layer is comprised of a material selected from the groupconsisting of HDP-oxide, HDP-FSG and HDP-PSG.
 20. The method of claim13, wherein said metal lines comprise said lower barrier layer selectedfrom the group consisting of Ti, TiN and Ti/TIN, a middle layercomprised of a material selected form the group consisting of AlCu andAlSiCu, and said upper etch stop layer is an ARC selected from the groupconsisting of TiN and Ti/TiN.
 21. The method of claim 13, wherein saidmetal via plugs are comprised of a metal selected from the groupconsisting of tungsten, aluminum, Cu, and AlCu.
 22. The method of claim13, wherein said metal lines comprise said lower barrier layer selectedfrom the group consisting of Ti and TiN, a middle layer of AlCu, andsaid upper etch stop layer is a TiN ARC; said second oxide layer isHDP-oxide; said etch barrier layer is SiN; and said metal via plugs aretungsten.
 23. A method of forming via plugs in a semiconductor device,comprising the steps of: providing a semiconductor structure having anupper first oxide layer and at least two borderless metal lines formedon said upper oxide layer; said metal lines being spaced apart greaterthan about 0.23 μm and each having a lower barrier layer and an upperanti-reflective coating etch stop layer; depositing a second oxide layerover said first oxide layer and said pair of metal lines by ahigh-density plasma (HDP) process; forming an etch barrier layer oversaid second oxide layer; said etch barrier layer being comprised of amaterial selected from the group consisting of SiN, SiON, H-rich SiN,and Si-rich SiN; planarizing said structure using a chemical-mechanicalpolish process to form self-aligned openings in said etch barrier layerover said metal lines; depositing and patterning a third oxide layerover said planarized structure to form via openings through said etchbarrier layer openings to said upper etch stop layers on said metallines; and forming metal via plugs in said via openings.
 24. The methodof claim 23, wherein said lower barrier layer is comprised of a materialselected from the group consisting of Ti, TiN and Ti/TiN.
 25. The methodof claim 23, wherein said middle layer is comprised of a materialselected from the group consisting of AlCu and AlSiCu.
 26. The method ofclaim 23, wherein said upper anti-reflective coating etch stop layer iscomprised of a material selected from the group consisting of TiN, Ti,and Ti/TiN.
 27. The method of claim 23, wherein said second oxide layeris comprised of a material selected from the group consisting ofHDP-oxide, HDP-FSG and HDP-PSG.
 28. The method of claim 23, wherein saidmetal lines comprise said lower barrier layer selected from the groupconsisting of Ti and TiN, a middle layer of AlCu, and said upperanti-reflective coating etch stop layer is a TiN ARC.
 29. The method ofclaim 23, wherein said metal via plugs are comprised of a metal selectedfrom the group consisting of tungsten, aluminum, Cu, and AlCu.
 30. Themethod of claim 23, wherein said metal lines comprise said lower barrierlayer selected from the group consisting of Ti and TiN, a middle layerof AlCu, and said upper anti-reflective coating etch stop layer is a TiNARC; said second oxide layer is HDP-oxide; said etch barrier layer isSiN; and said metal via plugs are tungsten.